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| Stratix II EP2S60 DSP Development Board DS-S29804 Data Sheet Features The Stratix(R) II EP2S60 DSP development board is included with the DSP Development Kit, Stratix II Edition (ordering code DSP-DEVKIT-2S60). This board is a development platform for high-performance digital signal processing (DSP) designs, and features the Stratix II EP2S60 device in a 1020-pin package. Components Analog I/O Two 12-bit 125-MHz A/D converters Two 14-bit 165-MHz D/A converters One 8-bit, 180 megapixels-per-second triple D/A converter for VGA output One 96-KHz Stereo Audio coder/decoder (CODEC) Memory subsystem 1 MByte of 10-ns asynchronous SRAM configured as a 32-bit bus 16 MBytes of flash memory configured as an 8-bit bus 32 MBytes of SDRAM memory configured as a 64-bit bus CompactFlash connector supporting ATA and IDE access modes Configuration options On-board configuration using 16 MBytes of flash memory and an Altera(R) EPM7256 MAX(R) device Download configuration data using an USB BlasterTM download cable Single-ended or differential inputs and outputs accessed via a Mictor connector Dual seven-segment display Four user-defined push-button switches One female 9-pin RS-232 connector 10/100 Ethernet MAC/PHY Eight user-defined LEDs Socketed 100-MHz oscillator Single 16-V DC power supply (adapter included) Active heat sink Altera Corporation October 2004 1 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Debugging Interfaces One Mictor-type connector for Agilent and Tektronix logic analyzers Several 0.1-inch headers Expansion Interfaces Two connectors for Analog Devices A/D converter daughter cards Connector for Texas Instruments Evaluation Module (TI-EVM) daughter cards Two Expansion Prototype connectors General Description The Stratix II EP2S60 DSP development board provides a hardware platform that designers can use to start developing DSP systems based on Stratix II devices. Combined with DSP intellectual property (IP) from Altera and Altera Megafunction Partners Program (AMPPSM) partners, users can quickly develop powerful DSP systems. Altera's unique OpenCore(R) Plus technology allows users to evaluate MegaCore(R) functions in hardware prior to licensing them. DSP Builder (version 2.2.0 or higher) includes a library for the Stratix II EP2S60 DSP development board. This library allows algorithm development, simulation, and verification on the board, all from within the MathWorks MATLAB/Simulink system-level design tool. Additionally, the Stratix II DSP development board includes a Texas Instruments' EVM (cross-platform) daughter card connector, which enables development and verification of FPGA co-processors for offloading and accelerating compute-bound algorithms from programmable DSP processors. 2 Preliminary Altera Corporation General Description Components & Interfaces Figure 1 shows a top view of the board components and interfaces. Figure 1. Stratix II EP2S60 DSP Development Board Components & Interfaces D/A External Clock Input (J12) External Clock Inputs (J10, J11) VGA Connector (J35) 40-Pin Connectors for Analog Devices A/D Converters (J5, J6) A/D Converter Clock Selector (J3, J4) Power Regulator (U22) ADC A Input SMA Connector (J1) 9-Pin RS-232 Connector (J9) Socketed 100-MHz Oscillator (Y1) Mictor Connector (J20) Joint Test Action Group (JTAG) Connectors (J21, J13) 8-Pin DIP Switch (SW2) 16.0-V DC Power Supply Connector (J22) ADC B Input SMA Connector (J2) DAC A Output SMA Connector (J15) DAC B Output SMA Connector (J17) Line In (J7) Line Out (J8) Amplified Line Out Audio Connector (J9) Expansion Prototype Connector (J23, J24, J25) Configuration-Status LEDs (LED1-LED4) Expansion Prototype Connector (J26, J27, J28) Dual Seven-segment Display (U12, U13) D/A Converter Clock Selector (J18 , J19) Compact Flash (CON1) (on Reverse Side of Board) Power Switch (SW9) Ethernet (RJ-45) Connector (RJ1) User LEDs (D1-D8) CONF_DONE LED (LED5) User Push-button Switches (SW4, SW5, SW6, SW7) Note to Figure 1: (1) A TI-EVM/FPDP connector (J31, J33) is found on the reverse side of the board. Altera Corporation 3 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 1 describes the components on the board and the interfaces it supports. Table 1. Stratix II EP2S60 DSP Development Board Components & Interfaces (Part 1 of 2) Component/ Interface Components Stratix II device MAX Device A/D converters D/A converters 1 MByte SRAM 16 MBytes of flash memory 32 MBytes of SDRAM SMA external clock input connectors FPGA PLD I/O I/O Memory Memory Memory Input U18 U10 U1, U2 U14, U15 U43, U44 U17 U39, U40 J10, J11, J12 U12, U13 SW4, SW5, SW6, SW7 D1 - D8 LED7 LED5 J29 EP2S60 Stratix II device Type Board Designation Description EPM7256ETC144 device Two 12-bit 125-MHz A/D converters Two 14-bit 165-MHz D/A converters 1 MByte of 10-ns asynchronous SRAM configured as a 32-bit bus. 16 Mbytes of flash memory configured as an 8-bit bus. 32 MBytes of SDRAM memory configured as a 64-bit bus SMA connectors for inputs of external clock signals, terminated in 50 . Dual seven-segment display. Four push-button switches, which are user-defined as logic inputs. Eight user-defined LEDs. LED that illuminates when power is supplied to the board. LED that illuminates upon successful configuration of the Stratix II device. DB9 connector, configured as a DTE serial port. The interface voltages are converted to 3.3-V signals and brought to the Stratix II device, which must be configured to generate and accept transmissions. Socketed on-board 100-MHz oscillator. Board adapter for included 16-V DC power supply JTAG Connector used to configure the Stratix II device directly JTAG connector used to configure the configuration controller Dual seven-segment Display display Push-button switches User-defined LEDs Power-on LED CONF_DONE LED RS-232 connector I/O Display Display Display I/O 100-MHz oscillator Single 16-V DC power supply Clock Input Y1 J22 (adapter) J21 Stratix II device Joint I/O Test Action Group (JTAG) Connector Configuration controller JTAG Connector I/O J13 4 Preliminary Altera Corporation General Description Table 1. Stratix II EP2S60 DSP Development Board Components & Interfaces (Part 2 of 2) Component/ Interface VGA D/A Converter Audio CODEC CompactFlash card connector I/O I/O I/O Type Board Designation U45 U5 CON1 Description One 8-bit, 180 megapixels-per-second triple D/A converter for VGA output 96-KHz stereo audio CODEC CompactFlash card connector Debugging Interfaces Mictor connectors I/O J20 One Mictor header connected to 33 pins on the Stratix II device (32 data signals, 1 clock signal) for use with an external logic analyzer. Expansion Interfaces Analog Devices connector (1) TI-EVM connectors Expansion Expansion J5, J6 J31, J33 J23 - J25, J26 - J28 Interface to Analog Device's A/D converters via two 40pin connectors. Interface to the TI-EVM. (The connectors are on the reverse side of the board.) The board provides two custom interfaces to daughter cards via 74-pin headers. (These pins can also be used for general I/O.) These connectors are referred to on the board as "Santa Cruz Daughter Card 1" and "Santa Cruz Daughter Card 2" Note to Table 1: (1) These headers can be used to interface to Analog Devices A/D converter evaluation boards. They are designated as J5 and J6, and interface to Analog Devices AD6645/9433/9430 external A/D converters. Expansion Prototype Expansion Connectors Environmental Requirements The Stratix II EP2S60 DSP development board must be stored between -40 C and 100 C. The recommended operating temperature is between 0 C and 55 C. 1 The Stratix II EP2S60 DSP development board can be damaged without proper anti-static handling. f The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. Depending on the specific requirements of your application, this level of cooling may not be necessary. Refer to "Install the Active Heat Sink" on page 49 for more information. Altera Corporation 5 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Using the Board When power is applied to the board and SW9 is in the "ON" position, the Power-on LED (LED7) illuminates. At that time, the MAX device (U10) programs the Stratix II device (U18) from one of 4 flash memory spaces reserved for configuration information. If configuration is successful, the CONF_DONE LED (LED5) illuminates. 1 If the Stratix II device is programmed with a design in one of the user configuration memory spaces or using the JTAG connector (J21), both the CONF_DONE LED (LED5) and the USER LED (LED1) illuminate. For more information, refer to "Configuration-Status LEDs" on page 18. To configure the board with a new design, the designer should perform the following steps, explained in detail in this section. 1. 2. Apply power to the board. Re-configure the Stratix II device. Apply Power Apply power to the board by connecting the 16-V DC power supply adapter, provided in the DSP Development Kit, Stratix II edition, to the on-board power adapter connector (J22), and switching SW9 to the ON position. All of the board components draw power either directly from this 16-V supply or from the 3.3-V, 1.2-V, and 5-V regulators that are powered by the 16-V supply. 1 The 3.3-V supply provides VCCIO to the Stratix II device and all LVTTL board components. The 1.2-V supply provides VCCINT to the Stratix II device. When power is applied to the board, the Power On LED (LED7) illuminates. c The Stratix II EP2S60 device, the A/D and D/A converters, and power regulator U22 become hot as the board is used. Because their surface temperature may significantly increase, do not touch these devices while power is applied to the board. 6 Preliminary Altera Corporation Non-Volatile Configuration Configure the Stratix II Device Directly You can configure the Stratix II device directly, without turning off power, using the Quartus(R) II software and the USB Blaster cable, as follows. 1. 2. Attach the cable to J21, also labeled "JTAG Stratix II". Open a Quartus II SRAM Object File (.sof), which starts the Quartus II Programmer. Select USB Blaster as the hardware. Set the mode to JTAG. Click Start. 3. 4. 5. After successful configuration, the CONF_DONE LED (LED5) illuminates. f Non-Volatile Configuration Refer to Quartus II Help for instructions on how to use the USB Blaster cable. The designer must reconfigure the Stratix II device each time power is applied to the Stratix II DSP development board. For designers who want to power up the board and have a design immediately present in the Stratix II device, the board has a non-volatile configuration scheme. This scheme consists of a configuration controller (U10), which is an Altera EPM7256 PLD, and flash memory. The configuration controller device is non-volatile (i.e., it does not lose its configuration data when the board is powered down) and it comes factory-programmed with logic that configures the Stratix II EP2S60F1020C4 device (U18) from data stored in flash (U17) on power-up. Upon power-up, the configuration controller begins reading data from the flash memory. The flash memory, Stratix II device, and configuration controller are connected so that data from the flash configures the Stratix II device in fast passive-parallel mode. Altera Corporation 7 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Configuration Data The Quartus II software can produce Hexadecimal (Intel format) Output (.hexout) files suitable for download and storage in the flash memory as configuration data. The designer can create a HEXOUT file using the Quartus II software in one of the following ways: Create a HEXOUT file at the end of compilation Convert a SRAM Object File (.sof) to a HEXOUT file. Write a HEXOUT file at Compilation To set up a project so that the Quartus II software writes a HEXOUT file at the end of compilation, perform the following steps: 1. 2. 3. 4. 5. Choose Settings (Assignments menu). Click Device under Compiler Settings. Click Device and Pin Options. Click the Programming Files tab. Turn on the Hexadecimal (Intel-Format) Output File (.hexout) option. With this option turned on, the Quartus II software generates a .hexout at the end of a successful compilation. Convert a SOF to a HEXOUT File The designer can convert a SOF to a HEXOUT file by performing the following steps in the Quartus II software: 1. 2. Choose Convert Programming Files (File menu). Under Output programming file, choose Hexadecimal (IntelFormat) Output File for SRAM (.hexout) from the Programming file type list box. Specify an output file name in the File name box. The default is output_file.hexout. Click SOF Data under Input files to convert. Click Add File. Browse to the SOF to convert and click OK. The Quartus II software converts the file and saves the output file to the specified directory. 3. 4. 5. 6. 8 Preliminary Altera Corporation Non-Volatile Configuration 1 Intel-format HEXOUT files contain data that is not actually written to the flash memory. The Write2Flash executable file (provided in the Factory & User Configurations The configuration controller can manage four separate Stratix II device configurations as HEXOUT data stored in flash memory: three user designs and a factory design. On power-up, the configuration controller reads one of the four (user or factory) designs from the flash memory and programs the Stratix II device accordingly. The user can select which design the Stratix II device is programmed with by setting the DIP switches on SW2. DIP switches 1 through 3 on SW2 select one of four possible Stratix II configuration images upon power-up. When DIP switch 4 is in the "OPEN" position the configuration controller is enabled. If DIP switch 4 is in the "OPEN" position and there are no valid user-defined images, the Stratix II device is programmed with the factory configuration. Table 2 shows the DIP switch combinations used to select the available images. See "Non-Volatile Configuration" on page 7 for more details. 1 An alternative method of configuring the device with the factory design is to press push-button switch SW3. Table 2. Configuration DIP Switch (SW2) Combinations Image User0 User1 User2 Factory Switch 1 Closed Open Closed Open Switch 2 Closed Closed Open Open Switch 3 Closed Closed Closed Open Switch 4 Open Open Open Open 1 Switch 4 must be set to "OPEN" to enable the configuration controller. f To download a Quartus II-generated HEXOUT file to the flash memory on the board, refer to the Nios II Flash Programmer User Guide included on the DSP Development Kit, Stratix II Edition version 1.0.0 CD-ROM. Altera Corporation 9 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet The Factory Design When the Stratix II device is programmed with the factory design, LEDs D5 through D8 behave as a binary counter that counts down to zero. This is a power-up indication that the board is functional and the device was successfully programmed with the factory design. Along with the LED counter, the factory design includes two blocks of IP generated by the Altera NCO Compiler. One of these oscillators is running at 10 times the frequency of the other, but both of them have the same amplitude, covering 13 bits of dynamic range. Two sine waves generated by these blocks are added together and the output is converted from a 2's complement representation into unsigned integer format. This combined sine wave signal of 14-bits dynamic range is sent to a 14-bit D/A converter. When the analog output of the D/A converter is connected, via the included SMA cable, with the analog input of one of the 12-bit A/D converters, the A/D converter's digital output is looped back to the Stratix II device. The design converts this loopback input from 2's complement format to unsigned integer format. The converted loopback data is captured by an instance of the SignalTap(R) II logic analyzer in the design for display and analysis. f For step-by-step instructions on how to use the factory design to test the functionality of the board, refer to the DSP Development Kit, Stratix II Edition Getting Started User Guide. 10 Preliminary Altera Corporation Non-Volatile Configuration Functional Description This section describes the elements of the Stratix II EP2S60 DSP development board. Figure 2 shows a block diagram of the board. Figure 2. Stratix II EP2S60 Development Board Block Diagram A/D Converter A/D Converter 12 256K x 36 SRAM 12 256K x 36 SRAM Mictor Connector D/A Converter D/A Converter 14 Stratix II EP2S60 Device Analog Devices A/D Converters Connector Prototyping Area Dual Seven-Segment Display TI-EVM Connector 0.1-inch Digital I/O Headers 14 80-MHz Oscillator JTAG Connector RS-232 LEDs Configuration Controller 32 Mbit Flash 5.0 V SMA External Clock Input SMA External Clock Output Regulators Vccint (1.5 V) Vccio (3.3-V) DIP Switches Pushbutton Switches Altera Corporation 11 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Power The 16-layer development board has 10 signal layers and 6 ground/VCC planes. The board is powered from a single, well-regulated 16-V supply. Regulators on the board are used to develop the VCCINT (1.2 V), VCCIO (3.3 V), and VCC5 (5.0 V) voltages. The board includes a Power-on LED that indicates the presence of VCCIO. The following board elements are powered by the 3.3 V supply: LEDs Switches Crystal oscillator Table 3 lists the reference information for the 16-V power supply, which connects from the wall socket to the DSP development board. Table 3. Power Supply Specifications Item Board reference Part number Device description Description N/A (power supply adapter) TR9KT3750LCP-Y Switching power supply, Input: 100-240 V, ~1.2 A max., 50-60 Hz Output: +16 V, 3.75 A, 60 W max. GlobTek Inc. www.globtek.com Manufacturer Manufacturer web site Clocks & Clock Distribution Table 4 lists the clocks and their signal distribution throughout the board. Table 4. Clock Distribution Signals (Part 1 of 3) Signal Name dac_PLLCLK1 dac_PLLCLK1_n dac_PLLCLK2 Comes From Stratix II device pin B15 (PLL5_OUT0p) Stratix II device pin C15 (PLL5_OUT0n) Stratix II device pin C16 (PLL5_OUT1p) Goes To DAC A (U14 pin 28) DAC A (U14 pin 28) DAC B (U15 pin 28) (2) 12 Preliminary Altera Corporation Non-Volatile Configuration Table 4. Clock Distribution Signals (Part 2 of 3) Signal Name dac_PLLCLK2_n sdram_CLK adc_PLLCLK1 adc_PLLCLK2 audio_CLK pld_MICTORCLK pld_CLKOUT Comes From Stratix II device pin D16 (PLL5_OUT1n) Goes To DAC B (U15 pin 28) (2) Stratix II device pin AK16 SDRAM (U39 U40 pins 68) (PLL6_OUT0p) Stratix II device pin B18 (PLL11_OUT0p) Stratix II device pin D18(PLL11_OUT0n) Stratix II device pin AL18(PLL12_OUT0p) Stratix II device pin M25 Stratix II device pin J14 ADC A (U1 pins 8, 7) (1) ADC B (U2 pins 8, 7) (1) Audio CODEC (U5 pin 25) Mictor Connector (J20 pin 5) PROTO1 (J25 pin 11) and PROTO2 (J28 pin 11) via a buffer (U7) Stratix II device pins AM17 and A16 Stratix II device pins AL17 and B16 PROTO1 (J25 pin 9) and PROTO2 (J28 pin 9) via a buffer (U7) CPLD (U10 pin 125) ADC A (U1 pins 8, 7) and B (U2 pins 8, 7) (1) DAC A (U14 pin 28) and B (U15 pin 28) (2) pld_CLKIN0,pld_CLK IN1 pld_CLKIN0_n,pld_C LKIN1_n proto1_OSC, proto2_OSC cpld_CLKOSC adc_CLK_IN1, adc_CLK_IN2 dac_CLKIN1, dac_CLKIN2 pld_CLKFB adc_CLK_IN1_n, adc_CLK_IN2_n dac_DACCLKIN1, dac_DACCLKIN2 pld_DACCLKIN 100-MHz oscillator External CLKIN_n input (J11) 100-MHz oscillator 100-MHz oscillator 100-MHz oscillator 100-MHz oscillator pld_CLKOUT signal from Stratix II device pin U1 the Stratix II pin J14 External CLKIN_n input (J11) External DA_EXT_CLK input (J12) External DA_EXT_CLK input (J12) ADC A (U1 pins 8, 7) and B (U2 pins 8, 7) (1) DAC A (U14 pin 28) and B (U15 pin 28) (2) Stratix II device pin E16 Altera Corporation 13 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 4. Clock Distribution Signals (Part 3 of 3) Signal Name proto1_CLKOUT, proto2_CLKOUT Notes to Table 4: (1) (2) J3 and J4 control which clock is routed to the A/D converters. See Table 10 for details. J18 and J19 control which clock is routed to the D/A converters. See Table 16 for details. Comes From Goes To Stratix II device pins T32 and PROTO1 (J25 pin 13) PROTO2 (J28 pin 13) via T30 a buffer (U7) The Stratix II EP2S60 DSP development board can obtain a clock source from one or more of the following sources: The on-board crystal oscillator An external clock (through an SMA connector or a Stratix II pin) The board can provide independent clocks from both the enhanced and fast PLLs to the A/D converters, the D/A converters, and the other components that require stable clock sources. To implement this concept, the enhanced PLL5-dedicated pins drive the A/D converters and associated functions, and the enhanced PLL6-dedicated pins drive the D/A converters and associated functions. 14 Preliminary Altera Corporation Non-Volatile Configuration Figure 3 is a diagram of each clock and their distribution throughout the board. Figure 3. Clock Distribution 100-MHz Oscillator Configuration Controller Expansion Prototype Connector Clock Distribution 1 Clock Distribution 2 Expansion Prototype Connector CLK_IN_p SDRAM Stratix II EP2S60F1020C4 Device Audio CODEC CLK_IN_n Clock Distribution 3 ADC A Jumper CLK Buffer ADC A ADC B Jumper DA_EXT_CLK Clock Distribution 4 DAC A Jumper CLK Buffer ADC B DAC DAC B Jumper DAC Table 5 lists the reference information for the 100-MHz socketed oscillator. Table 5. 100-MHz Socketed Oscillator Reference Item Board reference Part number Device description Manufacturer Manufacturer web site Description Y1 ECS-UPO-8PIN 100MHz Oscillator ECS Inc. www.ecsxtal.com Altera Corporation 15 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet 1 Clock Distribution 1 source can be either the oscillator (Y1) or an external clock inserted using J10. To use an external clock signal, remove the crystal oscillator from its socket. Make sure to note the correct orientation of the oscillator before removing it. Board Components The following sections describe the development board components. Stratix II Device (U18) The Stratix II EP2S60 device on the board features 24,176 adaptive logic modules (ALMs) in a speed grade (-4) 1020-pin FineLine BGA(R) package. The device has 2,544,192 total RAM bits. f For more information on Stratix II devices, refer to the Stratix II Device Handbook. Table 6 describes the features of the Stratix II EP2S60F1020C4 device. Table 6. Stratix II Device Features Feature ALMs Adaptive look-up tables (ALUTs) M512 RAM Blocks (32 x 18 bits) M4K RAM Blocks (128 x 36 bits) M-RAM Blocks Total RAM bits DSP Blocks Embedded multipliers (based on 18 x 18 mode of operation) Enhanced PLLs Fast PLLs Maximum user I/O pins Package type Board reference Voltage EP2S60F1020 24,176 48,352 329 255 2 2,544,192 36 144 4 8 717 1020-pin FineLine BGA U18 1.2 V (internal), 3.3 V (I/O) 16 Preliminary Altera Corporation Board Components Switch Inputs The board has four push-button switches for user-defined logic input. Each push-button signal when pressed, drives logic low and when released goes back to driving logic high. Table 7 shows the pin-outs for the push-button switches. Table 7. Push-button Switch Pin-Outs Signal Name SW4 SW5 SW6 SW7 Stratix II Pin K14 J15 L13 J13 Altera Corporation 17 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Configuration-Status LEDs The configuration controller is connected to four status LEDs that show the configuration status of the board at a glance. You can tell which configuration, if any, was loaded into the FPGA at power-on by looking at the LEDs. If a new configuration is downloaded into the Stratix II device via the JTAG interface, then the USER LED (LED1) remains illuminated. The rest of the configuration-status LEDs turn off if the unused pins are configured as inputs, tri-stated for the Stratix II device. Table 8 shows the behavior of the configuration-status LEDs. Table 8. Configuration Status LED Indicators LED LED3 LED4 LED Name Loading Error Color Green Red Description This LED blinks while the configuration controller is actively transferring data from flash memory into the Stratix II FPGA. If the red Error LED is on, then configuration was not transferred from flash memory into the Stratix II device. This can happen if, for example, the flash memory contains neither a valid user or factory configuration. This LED turns on when the user configuration is being transferred from flash memory and stays illuminated when the user configuration data is successfully loaded into the Stratix II device. This LED turns on when the factory configuration is being transferred from flash memory and stays illuminated if the factory configuration was successfully loaded into the Stratix II device. LED1 User Green LED2 Factory Amber Dual Seven-Segment Display & LEDs A dual seven-segment display and two LEDs are provided. The segments illuminate if the Stratix II pin to which they are connected drives low. They appear unlit when the connected Stratix II device pin drives high. The LEDs illuminate if the connected Stratix II device pin drives high, and are unlit when the connected Stratix II device pin drives low. Table 9 shows the pin-outs for the seven-segment display and LEDs. Table 9. Seven-Segment Display & LED Pin-Outs (Part 1 of 2) Signal Dual Seven-Segment Display HEX_0A HEX_0B HEX_0C C4 C5 B5 Stratix II Pin 18 Preliminary Altera Corporation Board Components Table 9. Seven-Segment Display & LED Pin-Outs (Part 2 of 2) Signal HEX_0D HEX_0E HEX_0F HEX_0G HEX_0DP HEX_1A HEX_1B HEX_1C HEX_1D HEX_1E HEX_1F HEX_1G HEX_1DP Stratix II Pin B6 D7 C7 B8 B9 F9 E9 C10 C11 F11 F12 C12 B12 LEDs pld_LED0 (board designation: D1) pld_LED1 (board designation: D2) pld_LED2 (board designation: D3) pld_LED3 (board designation: D4) pld_LED4 (board designation: D5) pld_LED5 (board designation: D6) pld_LED6 (board designation: D7) pld_LED7 (board designation: D8) B4 D5 E5 A4 A5 D6 C6 A6 Altera Corporation 19 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Figure 4 shows the pin-outs for the seven-segment display. Figure 4. Pin-Out Diagram for the Dual Seven-Segment Display HEX_0A HEX_0F HEX_0B HEX_1F HEX_1A HEX_1B HEX_1G HEX_0G HEX_0D HEX_0C HEX_0E HEX_0DP HEX_1D HEX_1C HEX_1DP Altera Corporation A/D Converters The Stratix II EP2S60 DSP development board has two 12-bit A/D converters that produce samples at a maximum rate of 125 mega-samples per second (MSPS). The A/D subsystem of the board has the following features: The data output format from each A/D converter to the Stratix II device is in two's complement format. The circuit has a wideband, AC-coupled, differential input useful for IF sampling. The analog inputs are transformer-coupled to the A/D converter in order to create a balanced input. To maximize performance, two transformers are used in series. The Analog Devices data sheet for the AD9433 device describes the detailed operation of this circuit. Any required anti-aliasing filtering can be installed externally. If needed, users can purchase in-line SMA filters from a variety of manufacturers, such as Mini-Circuits (www.minicircuits.com). The transformer-coupled AC circuit has a lower 3-dB frequency, of approximately 1 MHz. 1 The clock signal that drives the A/D converters can originate from the Stratix II device, the external clock input, or the on-board 100-MHz oscillator. Jumper J3 controls which clock is used for ADC A and J4 is used 20 Preliminary HEX_1E Board Components to select the clock for ADC B. Table 10 explains how to select these three clock signals. The selected clock will pass through a differential LVPECL buffer before arriving at the clock input to both A/D converters Table 10. A/D Clock Source Settings J3, J4 Setting Pins 1 and 2 Pins 3 and 4 Pins 5 and 6 Clock Source Stratix II PLL circuitry OSC or External input clock positive OSC or External input clock negative Signal Name adc_PLLCLK1, adc_PLLCLK2 adc_CLK_IN1, adc_CLK_IN2 adc_CLK_IN1_n, adc_CLK_IN2_n Table 11 lists reference information for the A/D converters. Table 11. A/D Converter Reference Item Board reference Part number Device description Voltage Manufacturer Manufacturer web site Description U1, U2 AD9433BSQ 12-bit, 125-MSPS A/D converter 3.3-V digital VDD, 5.0-V analog VDD Analog Devices www.analog.com Altera Corporation 21 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet A/D Converter Stratix II Pin-Outs Tables 12 and 13 show the ADC A (U1) and ADC B (U2) Stratix II pin-outs. Table 12. ADC A (U1) Stratix II Pin-Outs Signal Name adcA_D0 (LSB) adcA_D1 adcA_D2 adcA_D3 adcA_D4 adcA_D5 adcA_D6 adcA_D7 adcA_D8 adcA_D9 adcA_D10 adcA_D11 (MSB) Stratix II Pin D1 D2 E3 E4 E1 E2 F3 F4 F1 F2 G3 G4 Table 13. ADC B (U2) Stratix II Pin-Outs Signal Name adcB_D0 (LSB) adcB_D1 adcB_D2 adcB_D3 adcB_D4 adcB_D5 adcB_D6 adcB_D7 adcB_D8 adcB_D9 adcB_D10 adcB_D11 (MSB) Stratix II Pin G1 G2 J3 J4 H1 H2 J1 J2 K3 K4 K1 K2 22 Preliminary Altera Corporation Board Components D/A Converters The Stratix II EP2S60 DSP development board has two D/A converters. The D/A subsystem of the board has the following features: The converters produce 14-bit samples at a maximum rate of 165 MSPS. The analog output from each D/A converter is single-ended. The D/A converters expect data in an unsigned integer format. 1 The D/A clock signals are output directly from the Stratix II device to the converters. Figure 5 shows the on-board circuitry after a D/A converter. The output of a D/A converter chip, DAC904, consists of a current source whose maximum value is 20 mA. This output is connected to ground on the board using a 51- resistor, creating a Thevenin equivalent voltage source of 1 V in series with a 51- resistor. When loaded with an external 50- termination, the output swing is reduced to 0.5 VPP. Additionally, there is a 27-pF capacitor in parallel with the output resistor resulting in a singlepole, low-pass filter with an upper 3-dB frequency of approximately 230 MHz when externally loaded. The output is then brought to an SMA connector. Figure 5. On-Board Circuitry after D/A Converter D/A Converter Output 27 pf 1 The development kit includes an SLP-50 anti-aliasing filter from Mini-Circuits. This filter provides a 55-MHz cut-off frequency. For systems with other bandwidth requirements, a variety of anti-aliasing filters are available from commercial manufacturers to suit the system requirements. Altera Corporation 23 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 14 shows the reference information for the anti-aliasing filter. Table 14. Anti-Aliasing Filter Reference Item Board reference Manufacturer Description Part number Manufacturer web site Description N/A Mini-circuits Anti-aliasing filter SLP-50 www.minicircuits.com Table 15 lists reference information for the D/A converters. Table 15. D/A Converter Reference Item Board reference Part number Device description Voltage Manufacturer Manufacturer web site Description U14, U15 DAC904 14-bit, 165-MSPS D/A converter 3.3-V digital VDD, 5.0-V analog VDD Texas Instruments www.ti.com Table 16 lists the clock source settings for the D/A converters. Table 16. D/A Clock Source Settings J18, J19 Setting Pins 1 and 2 Pins 3 and 4 Pins 5 and 6 Pins 7 and 8 Clock Source Stratix II PLL Circuitry Stratix II PLL Circuitry OSC or External input clock (J10) External input clock (J12) DA EXT CLK Signal Name dac_PLLCLK1, dac_PLLCLK2 dac_PLLCLK1_n, dac_PLLCLK2_n dac_CLK_IN1, dac_CLK_IN2 dac_DACCLKIN1, dac_DACCLKIN2 24 Preliminary Altera Corporation Board Components D/A Converter Stratix II Pin-Outs Tables 17 and 18 show the DAC A (U14) and DAC B (U15) Stratix II pin-outs. Table 17. D/A A (U14, J15) Stratix II Pin-Outs Signal Name dacA_D1 (MSB) dacA_D2 dacA_D3 dacA_D4 dacA_D5 dacA_D6 dacA_D7 dacA_D8 dacA_D9 dacA_D10 dacA_D11 dacA_D12 dacA_D13 dacA_D14 (LSB) Stratix II Pin U5 U6 U10 U11 V9 V10 V6 V7 V4 V5 W8 W9 W6 W7 Altera Corporation 25 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 18. D/A B (U15, J17) Stratix II Pin-Outs Signal Name dacB_D1 (MSB) (1) dacB_D2 dacB_D3 dacB_D4 dacB_D5 dacB_D6 dacB_D7 dacB_D8 dacB_D9 dacB_D10 dacB_D11 dacB_D12 dacB_D13 dacB_D14 (LSB) Note to Table 18: (1) The Texas Instruments (TI) naming conventions differ from those of Altera Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the most significant bit (MSB) and bit 14 as the least significant bit (LSB). Stratix II Pin W4 W5 Y6 Y7 Y8 Y9 Y10 Y11 AB5 AB6 AA10 AA11 AA6 AA7 SRAM Memory (U43 & U44) U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices. They are connected to the Stratix II device so they can be used by a Nios(R) II embedded processor as general-purpose memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. Table 19 lists the reference information for the SRAM memory. Table 19. SRAM Memory Reference Item Board reference Part Number Device description Manufacturer Manufacturer web site Description U43, U44 IDT71V416S10PH SRAM Memory IDT www.idt.com 26 Preliminary Altera Corporation Board Components Flash Memory (U17) U17 is a 16-Mbyte AMD AM29LV128M flash memory device connected to the Stratix II device. It can be used for two purposes: A Nios II embedded processor implemented in the Stratix II device can use the flash as general-purpose readable memory and non-volatile storage. The flash memory can hold a Stratix II device configuration file that is used by the configuration controller to load the Stratix II device at power-up. Hardware configuration data that implements the Nios II reference design is pre-stored in this flash memory. The factory programmed Nios II reference design, once loaded, can identify the 16-Mbyte flash memory in its address space, and can program new data (either new Stratix II configuration data, Nios II embedded processor software, or both) into flash memory. The Nios II embedded processor software includes subroutines for writing and erasing this specific type of AMD flash memory. Table 20 lists the reference information for the Flash memory. Table 20. Flash Memory Reference Item Board reference Part number Device description Manufacturer Manufacturer web site Description U17 AM29LV128MH103REI Flash Memory AMD www.amd.com SDRAM Memory (U39 and U40) The SDRAM devices (U39 and U40) are 2 Micron MT48LC4M32B2 devices with PC100 functionality and self refresh mode. The SDRAM is fully synchronous with all signals registered on the positive edge of the system clock. The SDRAM device pins are connected to the Stratix II device. An SDRAM controller peripheral is included with the Stratix II DSP Development Kit, allowing a Nios II processor to view the SDRAM devices as a large, linearly-addressable memory. Altera Corporation 27 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 21 lists the Stratix II device pin-outs for SDRAM device U39. Table 21. SDRAM Device (U39) Pin-Outs (Part 1 of 2) Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 Pin Number 25 26 27 60 61 62 63 64 65 66 24 21 22 23 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 Connects to Stratix II Pin AD11 AD13 AB13 AE14 AB14 AC14 AD14 AE10 AB15 AC16 AB16 AE13 AL9 AF11 AL4 AJ5 AH5 AM4 AG9 AH6 AH7 AH9 AM5 AK6 AJ6 AM6 AM7 AK7 AJ7 AM8 AJ10 AK8 28 Preliminary Altera Corporation Board Components Table 21. SDRAM Device (U39) Pin-Outs (Part 2 of 2) Pin Name DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CKE CS_N WE_N CLK Pin Number 34 36 37 39 40 42 45 47 48 50 51 53 54 56 16 71 28 59 19 18 67 20 17 68 Connects to Stratix II Pin AJ8 AM9 AF12 AG10 AF10 AG12 AJ11 AH11 AL10 AM10 AK12 AJ12 AM11 AM12 AK5 AG8 AH8 AL5 AK4 AL8 AL7 AL6 AK9 AK16 Table 22 lists the Stratix II device pin-outs for SDRAM device U40. Table 22. SDRAM Device (U40) Pin-Outs (Part 1 of 3) Pin Name A0 A1 A2 A3 A4 Pin Number 25 26 27 60 61 Connects to Stratix II Pin AD11 AD13 AB13 AE14 AB14 Altera Corporation 29 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 22. SDRAM Device (U40) Pin-Outs (Part 2 of 3) Pin Name A5 A6 A7 A8 A9 A10 A11 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 Pin Number 62 63 64 65 66 24 21 22 23 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 Connects to Stratix II Pin AC14 AD14 AE10 AB15 AC16 AB16 AE13 AL9 AF11 AH13 AG13 AF13 AG15 AL14 AJ14 AJ13 AM14 AL20 AH19 AJ19 AH20 AM21 AK21 AJ21 AM22 AJ23 AK22 AG22 AG23 AM23 AK23 AK24 AM24 AK25 30 Preliminary Altera Corporation Board Components Table 22. SDRAM Device (U40) Pin-Outs (Part 3 of 3) Pin Name DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM0 DQM1 DQM2 DQM3 RAS_N CAS_N CKE CS_N Pin Number 47 48 50 51 53 54 56 16 71 28 59 19 18 67 20 Connects to Stratix II Pin AH24 AH26 AG24 AM26 AM25 AJ26 AK26 AK13 AL13 AB12 AC12 AK4 AL8 AL7 AL6 Table 23 lists the reference information for the SDRAM memory. Table 23. SDRAM Memory Reference Item Board reference Part number Device description Manufacturer Manufacturer web site Description U39, U40 MT48LC4M32B2TG-7 SDRAM Memory Micron www.micron.com Altera Corporation 31 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Ethernet MAC/PHY (U16) The LAN91C111 (U16) is a mixed signal analog/digital device that implements protocols at 10 Mbps and 100 Mbps. The control pins of U16 are connected to the Stratix II device so that user logic (e.g., the Nios II processor) can access Ethernet via the RJ-45 connector (RJ1). Table 24 lists the reference information for the Ethernet MAC/PHY. Table 24. Ethernet MAC/PHY Reference Item Board reference Part Number Device description Manufacturer Manufacturer web site Description U16 LAN91C111-NE Ethernet MAC/PHY SMSC www.smsc.com CompactFlash Connector (CON1) The CompactFlash connector header (CON1) enables hardware designs to access a CompactFlash card. The following two access modes are supported: ATA (hot-swappable mode) IDE (IDE hard-disk mode) Most pins of CON1 connect to I/O pins on the FPGA. The following pins have special connections: Pin 13 of CON1 (VCC) is driven by a power MOSFET that is controlled by an FPGA I/O pin. This allows the FPGA to control power to the CompactFlash card for the IDE connection mode. Pin 26 of CON1 (CD1#) is pulled up to 5V through a 10-K resistor. This signal is used to detect the presence of a CompactFlash card. When the card is not present, the signal is pulled high through the pull-up resistor. Pin 41 of CON1 (RESET) is pulled up to 5V through a 10-K resistor, and is controlled by the EPM7128AE configuration controller. The FPGA can cause the configuration controller to assert RESET, but the FPGA does not drive this signal directly. 32 Preliminary Altera Corporation Board Components Table 25 provides CompactFlash pin-out details. Table 25. CompactFlash (CON1) Pin Table (Part 1 of 2) Pin on CompactFlash (CON1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CompactFlash Function (U60) GND D03 D04 D05 D06 D07 CS0# A10 ATA_SEL# A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 DO0 DO1 DO2 IOCS16# CD2# CD1# D11 D12 D13 D14 D15 CS1# GND AA3 AA1 Y2 W1 V2 AE3 AF1 AD12 AF3 AF4 AG1 Connects to (1) VCC (2) AD6 AD7 AA8 AA9 AE2 AD2 AE1 AB3 AB1 Y4 AD1 AB8 (3) AC15 AA2 AA4 Y5 AB2 AB4 AC9 Altera Corporation 33 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 25. CompactFlash (CON1) Pin Table (Part 2 of 2) Pin on CompactFlash (CON1) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes to Table 25: (1) (2) (3) (4) All pin numbers represent I/O pins on the FPGA, unless otherwise noted. This FPGA I/O pin controls a power MOSFET that supplies 5V VCC to CON1. This pin does not connect to the FPGA directly. RESET is driven by the EPM7256AE configuration controller device. CompactFlash Function (U60) VS1# IORD# IOWR# WE# INTRQ VCC CSEL# VS2# RESET (4) WAIT# INPACK# REG# DASP# PDIAG# DO8 DO9 D10 VSS AB10 AC2 AC1 AC6 AC4 Connects to (1) VCC (2) AC8 AB9 AE12 AC3 AC7 AB7 AE4 AF2 V3 W2 Y3 GND (3) Table 26 lists the reference information for the CompactFlash connector.. Table 26. CompactFlash Connector Reference Item Board reference Part Number Device description Manufacturer Manufacturer web site Description CON1 53856-5010 CompactFlash connector Molex www.molex.com 34 Preliminary Altera Corporation Board Components f For general information on CompactFlash, see www.compactflash.org. Mictor Connector (J20) The Mictor connector (J20) can be used to transmit up to 27 high-speed I/O signals with very low noise via a shielded Mictor cable. J20 is used as a debug port. Twenty-five of the Mictor connector signals are used as data, and two signals are used as clock input and clock output. Most pins on J20 connect to I/O pins on the Stratix II device (U18). For systems that do not use the Mictor connector for debugging the Nios II processor, any on-chip signals can be routed to I/O pins and probed at J20 via a Mictor cable. External scopes and logic analyzers can connect to J20 and analyze a large number of signals simultaneously. f For details on Nios II debugging products that use the Mictor connector, see www.altera.com. Figure 6 shows an example of an in-target system analyzer ISA-Nios/T (sold separately) by First Silicon Solutions (FS2) Inc. connected to the Mictor connector. For details see www.fs2.com. Figure 6. An ISA-Nios/T Connecting to the Mictor Connector (J20) J25 BUSY COMM RUN POWER 1 Five of the signals connect to both the JTAG pins on the Stratix II device (U18) and the Stratix II device's JTAG connector (J24). The JTAG signals have special usage requirements. You cannot use J20 and J24 at the same time. Figure 7 below shows connections from the Mictor connector to the Stratix II device. Figure 8 shows the pin-out for J20. Unless otherwise noted, labels indicate Stratix II device pin numbers. Altera Corporation 35 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Figure 7. Mictor Connector Signaling Mictor Connector (J20) JTAG Connector (J21) Stratix II Device (U18) 5 40 Figure 8. Debug Mictor Connector - J20 P 35 27 P 33 26 P 31 29 P 29 28 N 27 27 N 25 26 N 23 25 N 21 24 TR 19 S TT 17 DI T 15 MS T 13 CK M 11 27 TD 9O M 2 76 N 23 5 N 2 32 N C 1 N C Table 27 lists the reference information for the Mictor connector. Table 27. Mictor Connector Reference Item Board reference Part number Device description Manufacturer Manufacturer web site 37 VGA Interface (J35) The board contains a high density DP15 connector, which outputs VGA, as well as a Triple Video D/A converter which has the following features: 3 x 8 bit, 180 megapixels per second 2.5% gain matching 0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy 38 C N 2 C N LK 4 _C TR 64 P2 8 25 P 3.3 10 CC V 3.3 12 C VC 14 26 R 16 27 R 18 22 R 20 23 R 22 24 R 24 25 R 26 28 R 28 29 R 30 27 T 32 28 T 34 22 T 36 23 T Description J20 2-767004-2 Mictor connector Tyco www.tyco.com 36 Preliminary Altera Corporation Board Components Single 3.3-V power supply Table 28 shows the pin-outs for the VGA interface. Table 28. VGA Interface (U45, J35) Pin-Outs Signal vga_B0 vga_B1 vga_B2 vga_B3 vga_B4 vga_B5 vga_B6 vga_B7 vga_G0 vga_G1 vga_G2 vga_G3 vga_G4 vga_G5 vga_G6 vga_G7 vga_R0 vga_R1 vga_R2 vga_R3 vga_R4 vga_R5 vga_R6 vga_R7 vga_BLANK_n vga_CLOCK vga_HSYNC vga_VSYNC vga_SYNC_n Stratix II Pin B7 E7 E6 A7 C9 A8 C8 A9 E11 G10 G11 G12 D12 A11 B11 A12 D8 E8 F8 F10 A10 B10 D10 D11 G13 E13 F15 B14 F13 Altera Corporation 37 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 29 describes the device used to implement the VGA interface. Table 29. VGA Interface Device Reference Item Board reference Part number Device description Voltage Manufacturer Manufacturer web site Description U45 FMS3818KRC Triple Video D/A Converter 3.3 V Fairchild www.fairchildsemi.com Audio CODEC (U5) The board contains three stereo jack connectors, which serve as one stereo input, one amplified stereo output and one non-amplified stereo output. The stereo jacks are driven by a Stereo Audio CODEC running at 8-96 KHz. Table 30 shows the pin-outs for the CODEC. Table 30. Audio CODEC (U5) Pin-Outs Signal audio_BCLK audio_CS_n audio_SDIN audio_SCLK audio_MODE audio_DOUT audio_DIN audio_LRCIN audio_LRCOUT audio_CLK Stratix II Pin AG4 AH1 AH2 AH3 AH4 AJ1 AJ2 AG2 AG3 AL18 38 Preliminary Altera Corporation Expansion Interfaces Table 31 describes the device used to implement the CODEC. Table 31. Audio CODEC Device Reference Item Board reference Part number Device description Voltage Manufacturer Manufacturer web site Description U5 TLV320AIC23PW Stereo Audio CODEC, 8-96 KHz 3.3 V Texas Instruments www.ti.com Expansion Interfaces The Stratix II EP2S60 DSP development board includes the following interfaces: A TI-EVM/FPDP connector (J31, J33), located on the reverse side of the board An RS-232C Serial I/O interface (J29) Two 0.1-inch headers specifically designed to be used with external analog-to-digital devices made by Analog Devices Corporation (J6, J5) Two Altera Expansion Prototype Connectors (J23, J24, J25; J26, J27, J28) TI-EVM/FPDP Connector (J31, J33) The TI-EVM interface is specifically designed to work with TI boards that have the EVM interface. Refer to the Texas Instruments web site for details on which of their boards feature this connector. Table 32 lists the pin-outs for the TI-EVM and FPDP connectors. Table 32. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 1 of 4) TI-EVM Signal Name J31 evm_DX0 evm_DR0 evm_IAK evm_INUM0 J21 H22 K12 H13 Stratix II Pin Altera Corporation 39 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 32. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 2 of 4) TI-EVM Signal Name evm_CNTL0 evm_STAT0 evm_DMAC0 evm_CLKOUT2 evm_CLKX0 evm_FSX0 evm_CLKR0 evm_FSR0 evm_RESET evm_INT0 evm_INT1 evm_INT2 evm_INT3 Stratix II Pin L12 J12 H12 K11 J22 G22 K22 K21 J11 H11 L14 C13 B13 J33 evm_A2 evm_A3 evm_A4 evm_A5 evm_A6 evm_A7 evm_A8 evm_A9 evm_A10 evm_A11 evm_A12 evm_A13 evm_A14 evm_A15 evm_A16 evm_A17 evm_A18 evm_A19 evm_A20 B20 E19 C20 E20 A21 C21 A22 C22 D23 D21 F22 F23 A23 C23 C24 A24 A25 A26 D26 40 Preliminary Altera Corporation Expansion Interfaces Table 32. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 3 of 4) TI-EVM Signal Name evm_A21 evm_D0 evm_D1 evm_D2 evm_D3 evm_D4 evm_D5 evm_D6 evm_D7 evm_D8 evm_D9 evm_D10 evm_D11 evm_D12 evm_D13 evm_D14 evm_D15 evm_D16 evm_D17 evm_D18 evm_D19 evm_D20 evm_D21 evm_D22 evm_D23 evm_D24 evm_D25 evm_D26 evm_D27 evm_D28 evm_D29 evm_D30 evm_D31 Stratix II Pin C26 E24 C25 E27 E26 A27 A28 D27 C27 B29 A29 D28 E28 D19 B21 D22 B23 B25 D25 B27 C28 D20 B22 E22 B24 B26 E25 B28 C29 L21 G21 L18 J19 Altera Corporation 41 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Table 32. TI-EVM /FPDP Connector (J31, J33) Pin-Outs (Part 4 of 4) TI-EVM Signal Name evm_BE_n0 evm_BE_n1 evm_BE_n2 evm_BE_n3 evm_AWE_n evm_ARDY evm_ACE2_n evm_ARE_n evm_AOE_n evm_ACE3_n Stratix II Pin H20 L19 K19 G20 L20 H21 J20 K20 K18 E14 RS-232C Serial I/O Interface The board contains a DB9 connector (J29), which provides a bidirectional RS-232C serial I/O interface. The board contains the transceiver (U41), however the logic controller (UART) must be implemented in the Stratix II device. Table 34 describes the device used to implement the RS-232C interface. J29 is a standard DB-9 serial connector. This connector is typically used for communication with a host computer using a standard 9-pin serial cable connected to (for example) a COM port. Level-shifting buffers (U52 and U58) are used between J29 and the Stratix II device, because the Stratix II device cannot interface to RS-232 voltage levels directly. J29 is able to transmit all RS-232 signals. The Stratix II design may use only the signals it needs, such as J29's RXD and TXD. LEDs are connected to the RXD and TXD signals, giving a visual indication when data is being transmitted or received. Figure 9 shows the pin connections between the serial connector and the Stratix II device. 42 Preliminary Altera Corporation Expansion Interfaces Figure 9. Serial Connector J29 GND DTR1 RXD1 TXD1 DCD1 IN IN OUT OUT K13 L16 L17 H14 Connector Pin # 5 4 3 1 2 Function Direction Stratix II Pin # J19 Connector Pin # StratixII Pin # Direction Function 7 6 9 8 K17 K15 L15 K16 OUT OUT IN OUT RI1 CTS1 RTS1 DSR1 Table 33 shows the pin-outs for the RS-232C interface. Table 33. RS-232C Serial Interface Pin-Outs Signal TXD RXD DTR DCD DSR RI CTS RTS Stratix II Pin L17 L16 K13 H14 K16 K17 K15 L15 Table 34 lists reference information for the RS-232C transciever device. Table 34. RS-232C Interface Device Reference Item Board reference Part number Device description Voltage Manufacturer Manufacturer web site Description U41 MAX221E RS-232 transceiver 3.3 V Maxim www.maxim-ic.com Altera Corporation 43 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet Analog Devices Corporation External A/D Support The Stratix II EP2S60 DSP development board supports Analog Devices A/D converters via two 40-pin 0.1-inch digital I/O headers (J5, J6). These two dual-purpose digital I/O headers can support a maximum of the following three converters. Two AD9433 converters Two AD6645 converters One AD9430 converter Table 35 lists the pin-outs for the ADI connectors. Table 35. ADI Connector (J5, J6) Pin-Outs (Part 1 of 2) ADI Signal Name Adi_D0 Adi_D1 Adi_D2 Adi_D3 Adi_D4 Adi_D5 Adi_D6 Adi_D7 Adi_D8 Adi_D9 Adi_D10 Adi_D11 Adi_D12 Adi_D13 Adi_D14 Adi_D15 Adi_D16 Adi_D17 Adi_D18 Adi_D19 Adi_D20 Adi_D21 Adi_D22 Adi_D23 Stratix II Pin L3 L4 N4 N5 M3 M4 L1 L2 N2 N3 M1 M2 R2 R3 P1 P2 J6 J7 J8 J9 K8 K9 L9 L10 44 Preliminary Altera Corporation Expansion Interfaces Table 35. ADI Connector (J5, J6) Pin-Outs (Part 2 of 2) ADI Signal Name Adi_D24 Adi_D25 Adi_D26 Adi_D27 Adi_D28 Adi_D29 Adi_D30 Adi_D31 Adi_D32 Adi_D33 Stratix II Pin L7 L8 K6 K7 L5 L6 M10 M11 M8 M9 Expansion Prototype Connector (J23, J24, J25) Headers J23, J24, and J25 collectively form a standard-footprint, mechanically-stable connection that can be used (for example) as an interface to a special-function daughter card. f For a list of available expansion daughter cards that can be used with the Stratix II EP2S60 DSP development board refer to www.altera.com/devkits. The expansion prototype connector interfaces include: 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U19, U20, U21, U22 and U25) to protect the Stratix II device from 5 V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V. A buffered, zero-skew copy of the on-board OSC output from U2. A buffered, zero-skew copy of the Stratix II device's phase-locked loop (PLL)-output from U60. A logic-negative power-on reset signal. Five regulated 3.3-V power-supply pins (2 A total maximum load for both connectors. One regulated 5-V power-supply pin (1 A total maximum load for both connectors. Numerous ground connections. Figures 10 and 11 show connections from the expansion prototype connector to the Stratix II device. Unless otherwise noted, labels indicate Stratix II device pin numbers. Altera Corporation 45 Preliminary 46 Preliminary J24 GND 1 2 VCC5 Stratix II EP2S60 DSP Development Board Data Sheet (1) (2) (3) (4) RESET_n R31 R32 M32 N31 L32 11 M30 13 N29 15 L30 17 GND 19 9 10 N30 12 L31 14 M29 16 N28 18 L29 7 8 M31 5 6 P31 3 4 R30 1 2 GND M24 H30 G30 F30 E30 11 D32 13 14 D31 12 E29 9 10 F29 7 8 G29 5 6 H29 3 4 E31 Notes to Figure 11: Pin 1 J23 20 NC 22 GND K32 21 K31 23 K30 25 K29 27 J31 29 H32 31 G32 33 G31 35 16 GND 18 GND 20 GND Pin 1 J24 J23 (1) Vunreg (U54 pin 2) J25 1 GND GND GND GND 3 5 7 9 12 GND 14 GND 10 GND 8 6 4 2 NC +3.3V +3.3V 24 GND 26 GND 28 J32 30 GND 32 H31 34 NC 36 F32 F31 37 E32 39 38 L26 40 GND Pin 1 J25 Figure 10. Expansion Prototype Connector - J23, J24, J25 Figure 11. Expansion Prototype Connector Pin Information - J23, J24, J25 Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from the card to the Stratix II device (2) PROTO1_OSC (U2 pin 6) (4) PROTO1_CLKOUT (AC14) 13 +3.3V 15 +3.3V 17 +3.3V 19 (3) PROTO1_CLKIN (U2 pin 17) 11 Altera Corporation Expansion Interfaces Expansion Prototype Connector (J26, J27, J28) Headers J26, J27, and J28 collectively form a standard-footprint, mechanically-stable connection that can be used (for example) as an interface to a special-function daughter card. The expansion prototype connector interface includes: 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the Stratix II device. Each signal passes through analog switches (U27, U28, U29, U30 and U31) to protect the Stratix II device from 5-V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3 V. A buffered, zero-skew copy of the on-board OSC output (from U2). A buffered, zero-skew copy of the Stratix II device's phase-locked loop (PLL)-output (from U60). A logic-negative, power-on reset signal. Five regulated 3.3-V power-supply pins (2A total max load for both expansion prototype connectors). One regulated 5-V power-supply pin (1A total max load for both expansion prototype connectors). Numerous ground connections. Figures 12 and 13 show connections from the expansion prototype to the Stratix II device. Unless otherwise noted, the labels indicate Stratix II device pin numbers. Figure 12. Expansion Prototype Connector - J26, J27, J28 J27 Pin 1 J28 J26 Pin 1 Pin 1 Altera Corporation 47 Preliminary 48 Preliminary (1) (2) (3) (4) J26 GND AJ17 K26 L23 J26 H27 11 K24 13 12 14 9 10 7 8 J27 H28 K25 AK17 5 6 L24 3 4 K27 1 2 +V5 RESET_n AC27 AD27 Y23 Y25 1 3 5 7 9 AA27 11 Y27 13 W25 15 W27 17 GND 19 2 4 6 8 GND AC26 AD26 Y22 10 Y24 12 AA26 14 Y26 16 W24 18 W26 Stratix II EP2S60 DSP Development Board Data Sheet Notes to Figure 13: J28 (1) Vunreg (U54 pin 2) NC +3.3V +3.3V 1 3 5 7 9 2 4 6 8 GND GND GND GND 10 GND 12 GND 14 GND J27 20 NC W29 21 W28 23 V24 25 V23 27 V28 29 U28 31 U23 33 22 GND 24 GND 26 GND 28 V29 30 GND 32 U27 34 NC Unregulated voltage from AC to DC power transformer Clk from board oscillator Clk from the Stratix II device via buffer Clk output from card connected to the Stratix II device. (2) PROTO2_OSC(U2 pin 6) (3) PROTO2_CLKIN (U2 pin 17) 11 (4) PROTO2_CLKOUT (B14) 13 +3.3V 15 +3.3V 17 +3.3V 19 16 GND 18 GND 20 GND U22 35 M23 37 M22 39 36 L25 38 AF19 40 GND Figure 13. Expansion Prototype Connector -Pin Information for J26, J27, & J28 Altera Corporation Expansion Interfaces Install the Active Heat Sink The DSP Development Kit, Stratix II Edition includes a heat sink and fan combination, also known as an active heat sink. This active heat sink maintains the Stratix II device within its thermal operating range, independent of the design size, clock frequency, and operating conditions, allowing you to evaluate larger high-speed designs in hardware before completing the thermal analysis of your system. Depending on the specific requirements of your application, this level of cooling may not be necessary. For further information, refer to Application Note 355: Stratix II Device System Power Considerations. To mount the active heat sink to the board, perform the following steps: 1. Center the heat sink on top of the Stratix II FPGA. The active heat sink can be mounted in two directions; mount it so the wires are as close as possible to the J36 connector. When connected, these wires supply the 5 V DC power to the fan. Tilt the heat sink as shown in Figure 14, and attach the clip under the FPGA. f 2. Figure 14. Tilt the Heat Sink Altera Corporation 49 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet 3. Insert a thin, flat tool (small flat-head screwdriver, tweezers, or any clip tool) into the clip's pry hole, and use it to gently push the clip on the edge of the FPGA. Snap the clip down to secure the heat sink. See Figure 15. Figure 15. Attach the Clip 4. Attach the heat sink fan power connector to the J36 connector, for 5 V DC power. Remove the Active Heat Sink To remove the heat sink and fan from the board, perform the following steps: 1. Disconnect the heat sink fan power connector from the J36 connector. Insert the thin, flat tool into one of the clip's pry holes. Using the tool, slightly push away and lift the plastic clip from the FPGA to detach one side of the heat sink. Repeat step 2 on the other side of the plastic clip to remove the heat sink completely. 2. 3. 50 Preliminary Altera Corporation Expansion Interfaces 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright (c) 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation 51 Preliminary Stratix II EP2S60 DSP Development Board Data Sheet 52 Preliminary Altera Corporation |
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